A γ characteristic is a characteristic relating an input signal value to a display luminance in a display such as a cathode ray tube (CRT), a liquid crystal display (LCD), or the like.
In general, the luminance L of a CRT varies in proportion to an input signal value E of the CRT raised to the power of γ (L=KEγ: K is a constant). Therefore, in order to perform correct half-toning, a signal on which inverse correction for raising a number to the power of 1/γ has been previously performed needs to be applied to the CRT. This is γ correction.
In general, for example, as described in Japanese Patent Laid Open (Kokai) No. PH06-245221, in a method of γ correction, a translation table for all input points is stored in a read only memory (ROM). Using this translation table, translation has been performed.
However, since an enormous amount of data of the translation table is stored in a memory such as a ROM, a necessary memory capacity has been increased, and a circuit has been enlarged.
To cite another method of γ correction, for example, a nonlinear process can be performed using an approximated γ characteristic (hereinafter referred to as approximate linear γ characteristic) having eight break points as shown in FIG. 1. This method provides the advantage that a memory, such as a ROM, for storing a translation table requiring an enormous capacity becomes unnecessary.
The approximate linear γ characteristic as shown in FIG. 1 is divided into eight break point intervals, first to eighth intervals, and is a linear broken line having respective predetermined gradients (a1 to a8) in the intervals. For example, when an input signal is denoted by x, multiplication processes are performed as follows: a multiplication process for the first interval is a1×x1, a multiplication process for the second interval is a2×x2, and the like.
When a nonlinear signal is inputted, signals resulting from the multiplication processes for the respective intervals are summed, whereby a nonlinearly-processed signal resulting from approximate γ correction is formed.
FIG. 2 is a configuration diagram of a nonlinear process circuit 100 using the approximate linear γ characteristic shown in FIG. 1.
The nonlinear process circuit 100 includes a interval decision circuit 102 for determining an inputted nonlinear signal, eight process circuits 103 to 110 for performing respective processes for the intervals, an output signal selection circuit 111 for adding respective signals processed by these eight process circuits 103 to 110, and an approximate linear register circuit 112 for storing the respective gradients and the like for the intervals.
The interval decision circuit 102 is a circuit for detecting to which interval a nonlinear input signal outputted from the nonlinear circuit 101 belongs.
Each of the process circuits 103 to 110 is a circuit for multiplying a nonlinear signal by the gradient of the approximate linear line set in the approximate linear register circuit 112.
The output signal interval circuit 111 is a circuit for performing an addition process on all signals resulting from the multiplication processes performed by the respective process circuits 103 to 110.
The approximate linear register circuit 112 is a circuit for storing set values for signal processing in the respective process circuits 103 to 110.
For example, in the case where a nonlinear signal X3′ is inputted for the approximate linear γ characteristic shown in FIG. 1, the interval decision circuit 102 detects that the inputted nonlinear signal X3′ falls in the third interval.
The first process circuit 103 multiplies the gradient a1=(Y1−Y0)/(X1−X0) and input signal data (X1−X0) of the first process circuit 103. Accordingly, the first process circuit 103 outputs a signal (Y1−Y0).
The second process circuit 104 multiplies the gradient a2=(Y2−Y1)/(X2−X1) and input signal data (X2−X1) of the second process circuit 104. Accordingly, the second process circuit 104 outputs a signal (Y2−Y1).
The third process circuit 105 multiplies the gradient a3=(Y3−Y2)/(X3−X2) and input signal data (X3′−X2) of the third process circuit 105. Accordingly, the third process circuit 105 outputs a signal (X3′−X2)/(X3−X2)×(Y3−Y2).
In the fourth to eighth process circuits 106 to 110 other than the above, input signal data is zero. Accordingly, the output signals of the fourth to eighth process circuits 106 to 110 are zero.
Signals processed by these first to eighth process circuits 103 to 110 are added by the output signal interval circuit 111, thus outputting a nonlinearly-processed output signal. The nonlinearly-processed output signal in this case is (Y3′−Y0).
Thus, the nonlinear process circuit 100 does not require a memory such as a ROM. However, process circuits as many as the number of intervals are required. Moreover, the setting of the multiplication process of each process circuit must be individually performed, and the amount of information of set values within the approximate linear register circuit 112 is increased. Therefore, the nonlinear process circuit has been enlarged.